1. Field of the Invention
This invention relates to electronic circuits, and more particularly to a Tri-State output circuit which is particularly useful in integrated circuit devices.
2. Description of the Prior Art
Tri-State circuit elements are well-known in the prior art. The symbol for an active low Tri-State buffer is shown in FIG. 1a. Simalarly, the circuit diagram for an active high Tri-State buffer is shown in FIG. 1b. Referring to FIG. 1a, active low Tri-State buffer 10 receives a low enable input signal E on input lead 12, and a data input signal A on input lead 11. In response to the data and enable input signals A and E, buffer 10 provides an output signal Z on output lead 13. When the active low Tri-State buffer 10 is disabled by the application of a high enable signal E (i.e. logical 1, typically 5 volts), the output lead 13 is in the high impedance state, and is effectively disconnected from either ground or the positive voltage supply VCC connected to buffer 10. Conversely, when buffer 10 is enabled by a low enable signal E (i.e. a logical 0, typically 0 volts), the output signal Z on lead 13 is determined by the data input signal A applied to lead 11. Thus, with buffer 10 enabled, and a logical 0 data input signal A applied to buffer 10, buffer 10 will provide a logical 0 (i.e. ground) output signal Z. Conversely, with buffer 10 enabled and a logical 1 input signal A applied to buffer 10, buffer 10 will provide a logical 1 (i.e. VCC) output signal Z.
The active high Tri-State buffer 100 of FIG. 1b, operates in a similar fashion as the active low Tri-State buffer 10 of FIG. 1a with the exception that active high Tri-State buffer 100 is enabled by a high enable signal E, and disabled by a low enable signal E.
One prior art implementation of the active low Tri-State buffer 10 of FIG. 1a is shown in the schematic diagram of FIG. 2. As shown in FIG. 2, buffer 20 includes input terminal 21 for receiving the enable signal E. When Tri-State buffer 20 is disabled by the application of a logical one enable signal E, the logical one enable signal E is applied to one input lead of NOR gate 25a thereby causing NOR gate 25a to generate a logical zero signal on its output lead which is connected to the input lead of inverter 27a. Inverter 27a thus generates on its output lead a logical one output signal which is applied to the gate of P channel MOS transistor 28a, thus causing MOS transistor 28a to turn off. Simultaneously, the logical one enable signal E is applied to the input lead of inverter 24, thus causing inverter 24 to generate a logical zero signal on its output lead which in turn is applied to one input lead of NAND gate 25b. NAND gate 25b thus generates a logical one signal on its output lead which in turn is applied to the input lead of inverter 27b. Inverter 27b thus generates a logical zero signal on its output lead which is applied to the gate of N channel MOS transistor 28b, thus causing transistor 28b to turn off. With transistors 28a and 28b both turned off, output terminal 26 of Tri-State buffer 20 is effectively disconnected from both ground (connected to the source lead of MOS transistor 28b), and the positive supply voltage VCC (connected to terminal 29, which in turn is connected to the source terminal of MOS transistor 28a). Thus, with a logical one enable signal E applied to active low Tri-State buffer 20, output terminal 26 is essesentially "floating", and current is not sourced to or sinked from external circuitry (not shown) connected to terminal 26. This, Tri-State buffer 20 is effectively disabled.
Conversely, with a logical zero enable signal E applied to input terminal 21 of Tri-State buffer 20, buffer 20 is enabled and the output signal on lead 26 is determined by the data input signal A applied to input terminal 22. For example, with buffer 20 enabled by a logical zero enable signal E, and a logical zero input data signal A applied to terminal 22, inverter 23 provides a logical one signal on its output lead 23a, thus causing NOR gate 25a to provide a logical zero signal on its output lead. The logical zero output signal from NOR gate 25a is in turn applied to the input lead of inverter 27a. Inverter 27a thus provides a logical one output signal to the gate of MOS transistor 28a, thus causing transistor 28a to turn off. Simultaneously, the logical zero enable signal E is applied to the input lead of inverter 24, thus causing inverter 24 to provide a logical one signal on its output lead 24a which in turn is applied to one input lead of NAND gate 25b. The logical one signal on lead 23a is applied to the other input lead of NAND gate 25b, thus causing NAND gate 25b to generate a logical zero on its output lead. This logical zero output signal from NAND gate 25b is in turn applied to the input lead of inverter 27b, and inverter 27b thus generates a logical one signal on its output lead. This logical one signal on the output lead of inverter 27b is applied to the gate of N channel MOS transistor 28b, thus causing transistor 28b to turn on. Thus, with buffer 20 enabled by a logical zero enable signal E, and a logical zero data signal A applied to terminal 22, MOS transistor 28a is turned off and MOS transistor 28b is turned on, thus effectively connecting output terminal 26 to ground through MOS transistor 28b and disconnecting output terminal 26 from the positive supply voltage VCC connected to terminal 29, thus providing a logical zero output signal Z and allowing Tri-State buffer 20 to sink current from external circuitry (not shown) connected to terminal 26.
Conversely, with Tri-state inverter 20 enabled by a low enable signal E and with a logical one data signal A applied to terminal 22, inverter 23 provides a logical zero signal on its output lead 23a, and NOR gate 25a provides a logical one signal on its output lead, inverter 27a provides a logical zero signal on its output lead connected to the gate of P channel transistor 28a, thus causing transistor 28a to turn on. Simultaneously NAND gate 25b provides a logical one on its output lead, and inverter 27b provides a logical zero on its output lead connected to the gate of transistor 28b, thus causing transistor 28b to turn off. Thus, with buffer 20 enabled by a logical zero enable signal E, and a logical one data signal A applied to terminal 22, output terminal 26 is effectively connected to the positive supply voltage VCC and is disconnected from ground, thus allowing Tri-State buffer 20 to source current to external circuitry (not shown) connected to terminal 26.
The truth table depicting the operation of active low Tri-State buffer 10 of FIG. 1 is as follows:
______________________________________ E A Z ______________________________________ 0 0 0 0 1 1 1 1 High impedance 1 0 High impedance ______________________________________
The Tri-State circuit 20 of FIG. 2 requires, in its simplest implementation, a total of twelve transistors. For example, an inverter, such as any one of inverters 23, 24, 27a, and 27b, is comprised of two MOS transistors, as shown in FIGS. 4a and 4b. FIG. 4a shows the symbol for an inverter 40 having an input terminal 41 and an output terminal 42. FIG. 4b shows the MOS transistor implementation of the inverter 40. As shown on FIG. 4b, inverter 40, again having input terminal 41 and output terminal 42, is constructed by suitably connecting P channel MOS transistor 44 and N channel MOS transistor 45, with terminal 43 being connected to a positive voltage supply. Thus, inverter 40 requires two MOS transistors. Similarly, a NAND gate, such as NAND gate 25b of FIG. 2, requires four MOS transistors. As shown in FIG. 5a and FIG. 5b, NAND gate 50, having input leads 51 and 52 and output lead 53, is contructed utilizing P channel MOS transistors 54 and 55, and N channel MOS transistors 56 and 57, with terminal 58 being connected to a positive voltage supply. Futhermore, a NOR gate, such as NOR gate 25a of FIG. 2, requires four MOS transistors. As shown in FIGS. 6a and 6b, NOR gate 60 having input terminals 61 and 62 and output terminal 63, is constructed utilizing P channel MOS transistors 65 and 66, and N channel MOS transistors 67 and 68. Thus, the Tri-State inverter circuit 20 of FIG. 2 requires a total of 14 MOS transistors.
Furthermore, when the Tri-State buffer 20 of FIG. 2 is enabled, the transition time between the application of an input signal A to input terminal 22 and the receipt of its corresponding output signal Z on output terminal 26 is equal to four gate delays. In other words, the operation of P channel MOS transistor 28a in response to an input signal A occurs after the input data signal A is propagated through gates 23, 25a, 27a, and transistor 28a, a total of four gate delays. Similarly, the operation of N channel MOS transistor 28b in response to input data signal A is also four gate delays, the gate delays provided by gates 23, 25b, 27b, and transistor 28b.
Using output transistors 28a and 28b of suitable geometries, Tri-State inverter 20 of FIG. 2 is capable of sinking or sourcing a rather large amount of current (typically 3.2 milliamperes) from output terminal 26. This relatively high output driving current ability is useful for driving external circuitry (not shown) connected to terminal 26, and the Tri-State inverter 20 of FIG. 2 is thus useful as an output buffer between the internal components of an integrated circuit device and external circuitry.
Of importance, the resistivity of a semiconductor sample, including the resistivity of the current carrying channel of an MOS transistor, is inversely proportional to the mobility of the charge carriers within the channel. Thus, as described, for example, in a text by A. S. Grove entitled "Physics and Technology of Semiconductor Devices", John Wiley and Sons, Inc., 1967, pages 111-113, the resistivity of a P type semiconductor sample EQU .rho..sub.P =1/q.mu..sub.P P
where
.rho..sub.P =the resistivity of the P type semiconductor, in ohm-cm; PA1 q=the magnitude of charge of a hole, which is equal to the charge of an electron; PA1 .mu..sub.P =the mobility of a hole; and PA1 P=the P type impurity concentration. PA1 .rho..sub.N =the resistivity of the N type semiconductor, in ohm-cm; PA1 .mu..sub.N =the mobility of an electron; and PA1 N=the N type impurity concentration. PA1 R=the resistance of the sample; PA1 .rho.=the resistivity of the sample; PA1 L=the length of the sample; and PA1 A=the cross-sectional area of the sample.
Similarly, the resistivity of an N type semiconductor sample is EQU .rho..sub.N =1/q.mu..sub.N N
where
Thus, for a given impurity concentration of both P type and N type impurities EQU .rho..sub.P /.rho..sub.N =.mu..sub.N /.mu..sub.P
As described in the aforementioned text of Grove, the mobilities of electrons and holes are dependent on temperature and impurity concentration, and the mobility of electrons is typically about twice the mobility of holes, for a given temperature and impurity concentration.
The resistance of a sample of semiconductor material is defined as EQU R=.rho.L/A
where
Thus, for a given impurity concentration and temperature, in order to provide an N channel MOS transistor and a P channel MOS transistor having equal channel resistances, and thus equal current carrying abilities for a given set of gate, source, drain and substrate voltages, the cross-sectional area of the P channel transistor must be approximately twice the cross-sectional area of the N channel transistor.
One prior art active high Tri-State circuit is shown in the schematic diagram of FIG. 3. With a logical zero enable signal E applied to one input lead of NAND gate 31, the output signal from NAND gate 31 is a logical one, thus turning off P channel MOS transistor 36. Similarly, with a logical zero enable signal E applied to the input lead of inverter 34, inverter 34 provides a logical one signal on its output lead, which is connected to one input lead of NOR gate 32, thus causing NOR gate 32 to provide a logical zero signal on its output lead. This logical zero output signal from NOR gate 32 is applied to the gate of N channel MOS transistor 39, thus causing transistor 39 to turn off. With both transistors 36 and 39 turned off in response to a logical zero enable signal E, the Tri-State inverter 30 is disabled, and output terminal 38 is in the high impedance state.
Active high Tri-State 30 is enabled by a logical one enable signal E. With a logical one enable signal E and a logical zero data signal A applied to Tri-State buffer 30, the output signal from NAND gate 31 is a logical one, thus causing P channel transistor 36 to turn off. Simarlily, with a logical one enable signal E and a logical zero data signal A, the output signal from NOR gate 32 is a logical one, thus causing N channel MOS transistor 39 to turn on. With transistor 36 off and transistor 39 on, output terminal 38 is effectively disconnected from the positive supply voltage VCC applied to terminal 37 and is connected to ground. Thus, with buffer 30 enabled by a high enable signal E and with a logical zero data signal A, output terminal 38 is low and is capable of sinking current from external circuitry (not shown) connected to output terminal 38. Conversely, with a logical one enable signal E and a logical one data signal A applied to Tri-State buffer 30, the output signal from NAND gate 31 is a logical zero, thus causing P channel transistor 36 to turn on. Similarly, with a logical one enable signal E and a logical one data signal A, the output signal from NOR gate 32 is a logical zero, thus causing N channel MOS transistor 39 to turn off. With transistor 36 on and transistor 39 off, output terminal 38 is effectively connected to the positive supply voltage VCC applied to terminal 37 and is disconnected from ground. Thus, with buffer 30 enabled by a high enable signal E and with a logical one data signal A, output terminal 38 is high and is capable of sourcing current to external circuitry (not shown) connected to output terminal 38.
The truth table for active high Tri-State circuit 30 of FIG. 3 is as follows:
______________________________________ E A Z ______________________________________ 0 0 High impedance 0 1 High impedance 1 0 0 1 1 1 ______________________________________
When MOS transistors of typical dimensions are used to construct buffer 30, Tri-State buffer 30 is incapable of providing as much driving (i.e. source or sink) current to terminal 38 as Tri-State buffer 20 of FIG. 2 because buffer 30 does not include buffers between gates 31 and 32 and output transistors 36 and 39, respectively. Thus, gates 31 and 32 are incapable of providing as much drive current to output transistors 36 and 39 as compared to a circuit which includes buffers of high driving current capabilities connected between gates 31 and 32 and output transistors 36 and 39, respectively. Accordingly, output transistors 36 and 39 of buffer 30 are typically made of smaller size than the output transistors 28a and 28b of the buffer 20 of FIG. 2. Furthermore, with Tri-State buffer 30 enabled, the data signal A is capable of controlling the output signal Z after only two gate delays (i.e. the gate delays provided by gate 31 and transistor 36 and the gate delay provided by gate 32 and transistor 39). Accordingly, the Tri-State buffer 30 of FIG. 3 is typically faster than the Tri-State buffer 20 of FIG. 2, although the Tri-State buffer 20 of FIG. 2 is capable of sourcing and sinking greater amounts of current than is the Tri-State buffer 30 of FIG. 3. The Tri-State buffer 30 of FIG. 3 requires a total of twelve MOS transistors.